ipsec-vpn-server docker on proxmox

In order to get ipsec-vpn-server running on a lxc container in proxmox some issues needed to be solved.

Add this to your container config file:

lxc.cgroup.devices.allow=a

lxc.cap.drop=

lxc.mount.entry = /dev/ppp dev/ppp none bind,create=file

Reviving the batteries on the FSP EP1500 UPS

Last year in December I stumbled upon an FSP EP1500 UPS in a thrift store. It was missing its outer cardboard packaging but looked otherwise in pristine condition and supplied with usb and serial cable and plastic wrapping.

There was no price tag on the unit and I asked one of the clerks what they wanted for it. He suggested about 16 dollar which to me looked like a great bargain.

I bought it and got it home. Instructions said that to leave it to charge for 6 h before turning it on which I did.
I left it charging for about 24 h before trying to start it but no cigar, it was completely dead.
Attaching an energy monitor and measured that it pulled a couple of watts but nothing happened.

Next step was to disassemble it to check the insides and access the lead acid batteries. Investigating the date codes inside the machine gave date codes in the 2013 - early 2014 region. Still the unit looked clean and unused inside.

There were two 12V 9Ah Lead-Acid batteries in series (24 V) glued together. Measuring the voltage between the poles was a sad affair both giving about 0.5 V each. This means that the battery has gone into deep sleep and needed replacement.

I tried to connect one of them to a battery charger but it failed to sense that it was being connected to a battery at all.

As a last effort I decided to connect the battery terminals to my programmable power supply. Set the voltage to 14.40 V (2.4 V * 6 cells) and set the current limit very low, initially only 10 mA.

Almost no current was consumed, only about 2 mA. Still I left it on for a couple of minutes. I then measured voltage between the poles and it had risen with a couple of tenths of a Volt.

Given this slight, small spark of life I continued to charge it over multiple days. Slowly, slowly the voltage increased as did the current consumed. After about a week of charging the voltage had inched its way up to about 11 V and the current consumption to about 50 mA. I now connected the battery charger instead and now the battery was detected.
I continued to charge it at the minimum current (0.1 A) the charger allowed.
This took an additional 3 days or so but finally the battery reached the nominal max charge Voltage 14.70.
I still had no idea how much of the 9 Ah capacity that was retained.

The procedure was repeated for the other 12 V battery and it gave a similar charging response.

Now it was finally time to reassemble the unit and power it on. Lo and behold the UPS started as expected.

A power disconnect test without any load connected was conducted with the following graph:

The UPS has, how shall we say it, interesting features such as being able to power itself even though the battery percentage is 0. I also like the voltage raise observed. Runtime was 13492 seconds = 3 hours and 45 minutes.

Recharging gave the following graph.

Next up is to run the UPS with a 25% load. Its nominal capacity is 1500 VA / 900 W. I will hopefully post updates with those charts.

Why one should use asynchronous resets in a digital design (in FPGAs) - Part 2

I studied the reset matter a bit more.
This time the following questions are answered:

1. What happens if the reset signal is omitted from the sensitivity list in a process with an asynchronous reset?
2. What happens if the flip-flop (FF) is not reset in the asynchronous reset assignment?

The answer to question 1 is pretty simple, at least when using Altera Quartus II.
The example code looks like this:

  async_reset : process (Clk)
  begin
    if (Rst = '1') then
      FF_Q <= '0';
    elsif (rising_edge(Clk)) then
      FF_Q <= FF_D;
    end if;
  end process;

Compiling this will inform you that you've been a naughty boy forgetting the reset signal in the sensitivity list and proceeds to add the reset signal for you.
The generated logic is identical to the one where the reset signal is in the sensitivity list:

The result of question 2 is more interesting:
2. What happens if the flip-flop (FF) is not reset in the asynchronous reset assignment?

The example code looks like this:

  async_reset : process (Clk, Rst)
  begin
    if (Rst = '1') then
      -- Reset of FF_Q disabled purposefully
      -- FF_Q <= '0';
    elsif (rising_edge(Clk)) then
      FF_Q <= FF_D;
    end if;
  end process;

Synthesis produced the following result, without yielding any warning!

First of all the synthesiser is playing smart here:

The reset is actually active low here, it has moved a previous inverter into this logical block, that is why the implementation above looks a bit strange.

If reset is 1 the D input of the FF will maintain the current state.

If reset is 0 the D input of the FF will be controlled by the input.

The reset input of the FF is not connected at all.

This implementation reflects what was written, but probably not what was intended, and the compiler didn't even warn about it.

This is also important to understand if some flops are to be reset within a design and some not.
The typical pattern here is that you have some control logic manipulating a larger cloud of data logic.
The control needs to be reset while the data doesn't.

These flops cannot be generated within the same process!
You then need to have multiple synchronous processes:

The control process with the asynchronous reset statement:
 ctrl_async_reset : process (Clk, Rst)
  begin
    if (Rst = '1') then
      C_FF_Q <= '0';
    elsif (rising_edge(Clk)) then
      C_Q <= C_FF_D;
    end if;
  end process;

The data process lacking the asynchronous reset statement:
 data_no_async_reset : process (Clk)
  begin
    if (rising_edge(Clk)) then
      D_FF_Q <= D_FF_D;
    end if;
  end process;

No iSight on mac os sierra

I'm running a mac book air 2012.
After upgrading to Mac OS X Sierra I noticed that the iSight was no longer working.

Turns out I needed to reset the smc controller twice to get it working.
See https://support.apple.com/sv-se/HT201295 for more info.

Why one should use asynchronous resets in a digital design (in FPGAs)

Usage of reset in a digital design which is synchronous is mandatory.

Typical advice is that control logic needs to be reset whereas data paths can be omitted.

Resets can either be synchronous or asynchronous.

The recommended pattern for a global reset net is to apply asynchronous assertion and synchronous de-assertion of reset. The reset needs to be synchronized to the clock driving the flip-flop (FF).

In the actual design a reset can either be synchronous or asynchronous.

A synchronous reset controls the D input of the FF.

An asynchronous reset controls the Reset input of the FF.

A asynchronous reset in a design can be generated by the following VHDL-code:

  async_reset : process (Clk, Rst)

  begin

    if (Rst = '1') then

      FF_Q <= '0';

    elsif (rising_edge(Clk)) then

      FF_Q <= FF_D;

    end if;

  end process;

This generates the following post-fit implementation:

A synchronous reset in a design can be generated by the following VHDL-code.

synch_reset : process (Clk)

  begin

    if (rising_edge(Clk)) then

      if Rst = '1' then

        FF_Q <= '0';

      else

        FF_Q <= FF_D;

      end if;

    end if;

end process;

This generates the following post-fit implementation:

A (Field Programmable Gate Array) FPGA is implemented by multiple logical blocks that can be configured to realize logic. Each FF in such a block already has a reset input regardless if it is used or not.
As you can see in the images above, implementing synchronous resets will force the reset to use inputs, logic and routing resources that could be used for implementing logic.
This in turn make the design use more resources, waste more power and generate worse timing.

The example code for this article can be found at:
https://github.com/ErikAndren/reset-study

Playing Chrono Cross using Popstarter on the PS2

Popstarter is a cool hack on the official ps2 psx emulator to get various games working.
I've finally been able to enjoy Chrono Cross this way until half way in the game where Norris joins your party.
Then after the character naming screen the game goes all black, looping the same music piece over and over.
Apparently this is related to the character portrait.

Some genious realized that one can use a gameshark code to replace the offending portrait with another.
Said and done, create a CHEATS.txt next to your VMC files on the medium your are playing from.

Add $3006EE59 000E and you've replaced Norris portrait with Zappas.
This allows the game to continue.

Modding a bicycle-light with a solar-powered led

I modded a bicyclelight by ripping out the conventional lamp and battery.
Instead I mounted a garden-light with a solar cell on top.
As long as the bicycle is parked outside this should take care of itself.
The only drawback is that the light emitted is to weak to be useful for actually reflecting light.