Usage of reset in a digital design which is synchronous is mandatory.
Typical advice is that control logic needs to be reset whereas data paths can be omitted.
Resets can either be synchronous or asynchronous.
The recommended pattern for a global reset net is to apply asynchronous assertion and synchronous de-assertion of reset. The reset needs to be synchronized to the clock driving the flip-flop (FF).
In the actual design a reset can either be synchronous or asynchronous.
A synchronous reset controls the D input of the FF.
An asynchronous reset controls the Reset input of the FF.
A asynchronous reset in a design can be generated by the following VHDL-code:
async_reset : process (Clk, Rst)
begin
if (Rst = '1') then
FF_Q <= '0';
elsif (rising_edge(Clk)) then
FF_Q <= FF_D;
end if;
end process;
This generates the following post-fit implementation:
A synchronous reset in a design can be generated by the following VHDL-code.
synch_reset : process (Clk)
begin
if (rising_edge(Clk)) then
if Rst = '1' then
FF_Q <= '0';
else
FF_Q <= FF_D;
end if;
end if;
end process;
This generates the following post-fit implementation:
A (Field Programmable Gate Array) FPGA is implemented by multiple logical blocks that can be configured to realize logic. Each FF in such a block already has a reset input regardless if it is used or not.
As you can see in the images above, implementing synchronous resets will force the reset to use inputs, logic and routing resources that could be used for implementing logic.
This in turn make the design use more resources, waste more power and generate worse timing.
The example code for this article can be found at:
https://github.com/ErikAndren/reset-study
