Sunday, November 06, 2016

Why one should use asynchronous resets in a digital design (in FPGAs) - Part 2

I studied the reset matter a bit more.
This time the following questions are answered:

1. What happens if the reset signal is omitted from the sensitivity list in a process with an asynchronous reset?
2. What happens if the flip-flop (FF) is not reset in the asynchronous reset assignment?

The answer to question 1 is pretty simple, at least when using Altera Quartus II.
The example code looks like this:

  async_reset : process (Clk)
  begin
    if (Rst = '1') then
      FF_Q <= '0';
    elsif (rising_edge(Clk)) then
      FF_Q <= FF_D;
    end if;
  end process;

Compiling this will inform you that you've been a naughty boy forgetting the reset signal in the sensitivity list and proceeds to add the reset signal for you.
The generated logic is identical to the one where the reset signal is in the sensitivity list:



The result of question 2 is more interesting:
2. What happens if the flip-flop (FF) is not reset in the asynchronous reset assignment?

The example code looks like this:

  async_reset : process (Clk, Rst)
  begin
    if (Rst = '1') then
      -- Reset of FF_Q disabled purposefully
      -- FF_Q <= '0';
    elsif (rising_edge(Clk)) then
      FF_Q <= FF_D;
    end if;
  end process;

Synthesis produced the following result, without yielding any warning!
First of all the synthesiser is playing smart here:
The reset is actually active low here, it has moved a previous inverter into this logical block, that is why the implementation above looks a bit strange.

If reset is 1 the D input of the FF will maintain the current state.
If reset is 0 the D input of the FF will be controlled by the input.
The reset input of the FF is not connected at all.

This implementation reflects what was written, but probably not what was intended, and the compiler didn't even warn about it.

This is also important to understand if some flops are to be reset within a design and some not.
The typical pattern here is that you have some control logic manipulating a larger cloud of data logic.
The control needs to be reset while the data doesn't.

These flops cannot be generated within the same process!
You then need to have multiple synchronous processes:

The control process with the asynchronous reset statement:
 ctrl_async_reset : process (Clk, Rst)
  begin
    if (Rst = '1') then
      C_FF_Q <= '0';
    elsif (rising_edge(Clk)) then
      C_Q <= C_FF_D;
    end if;
  end process;

The data process lacking the asynchronous reset statement:
 data_no_async_reset : process (Clk)
  begin
    if (rising_edge(Clk)) then
      D_FF_Q <= D_FF_D;
    end if;
  end process;





Monday, October 31, 2016

No iSight on mac os sierra

I'm running a mac book air 2012.
After upgrading to Mac OS X Sierra I noticed that the iSight was no longer working.

Turns out I needed to reset the smc controller twice to get it working.
See https://support.apple.com/sv-se/HT201295 for more info.


Sunday, October 23, 2016

Why one should use asynchronous resets in a digital design (in FPGAs)

Usage of reset in a digital design which is synchronous is mandatory.

Typical advice is that control logic needs to be reset whereas data paths can be omitted.

Resets can either be synchronous or asynchronous.
The recommended pattern for a global reset net is to apply asynchronous assertion and synchronous de-assertion of reset. The reset needs to be synchronized to the clock driving the flip-flop (FF).

In the actual design a reset can either be synchronous or asynchronous.
A synchronous reset controls the D input of the FF.
An asynchronous reset controls the Reset input of the FF.

A asynchronous reset in a design can be generated by the following VHDL-code:

  async_reset : process (Clk, Rst)
  begin
    if (Rst = '1') then
      FF_Q <= '0';
    elsif (rising_edge(Clk)) then
      FF_Q <= FF_D;
    end if;
  end process;

This generates the following post-fit implementation:




A synchronous reset in a design can be generated by the following VHDL-code.

synch_reset : process (Clk)
  begin
    if (rising_edge(Clk)) then
      if Rst = '1' then
        FF_Q <= '0';
      else
        FF_Q <= FF_D;
      end if;
    end if;
end process;

This generates the following post-fit implementation:


A (Field Programmable Gate Array) FPGA is implemented by multiple logical blocks that can be configured to realize logic. Each FF in such a block already has a reset input regardless if it is used or not.
As you can see in the images above, implementing synchronous resets will force the reset to use inputs, logic and routing resources that could be used for implementing logic.
This in turn make the design use more resources, waste more power and generate worse timing.

The example code for this article can be found at:
https://github.com/ErikAndren/reset-study


Saturday, November 21, 2015

Playing Chrono Cross using Popstarter on the PS2

Popstarter is a cool hack on the official ps2 psx emulator to get various games working.
I've finally been able to enjoy Chrono Cross this way until half way in the game where Norris joins your party.
Then after the character naming screen the game goes all black, looping the same music piece over and over.
Apparently this is related to the character portrait.

Some genious realized that one can use a gameshark code to replace the offending portrait with another.
Said and done, create a CHEATS.txt next to your VMC files on the medium your are playing from.

Add $3006EE59 000E and you've replaced Norris portrait with Zappas.
This allows the game to continue.



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Monday, August 24, 2015

Modding a bicycle-light with a solar-powered led

I modded a bicyclelight by ripping out the conventional lamp and battery.
Instead I mounted a garden-light with a solar cell on top.
As long as the bicycle is parked outside this should take care of itself.
The only drawback is that the light emitted is to weak to be useful for actually reflecting light.




Saturday, May 30, 2015

Espp8266 + DS18B20 = Show temp using Ssids

Using ssids as a medium to transfer information is both fun and interesting.
Building upon my last post using the ESP8266 to transmit multiple ssids I hooked it up to a DS10B20 temperature sensor. 
Every time the temperature changes the ESP8266 creates a new ssids with the current temperature stored in the ssid string. 

In order to know which temperature is the most recent, the current uptime in seconds is prepended to the string. This is hacky but works.


Code is here:
https://github.com/ErikAndren/esp8266-DallasTempWifiAnnouncer

Sunday, May 24, 2015

Ssid announcer using an ESPP8266

The ESP8266 is an interesting, inexpensive platform which offers wifi capabilities and an 80 MHz CPU.
Recent advancements include arduino IDE compatibility.
This makes development quick and easy.

A quick demo I wrote was to loop over multiple SSIDs.
This can be used to announcing the schedule of an event.


Code is here: https://github.com/ErikAndren/esp8266-SsidAnnouncer